llvm::mca

Types

Name	Description
`CircularSourceMgr`	Default SourceMgr over a fixed instruction sequence with optional looping.
`CodeEmitter`	A utility class used to compute instruction encodings for a code region.
`Context`	Owns simulated hardware units and builds default MCA pipelines.
`CriticalDependency`	A critical data dependency descriptor.
`CustomBehaviour`	Target hook for dependencies not captured by the scheduling model.
`CycleSegment`	A sequence of cycles.
`DefaultResourceStrategy`	Default resource allocation strategy used by processor resource groups and processor resources with multiple units.
`DefaultSchedulerStrategy`	Default instruction selection strategy used by class Scheduler.
`DispatchStage`	Implements the hardware dispatch logic of an instruction pipeline.
`EntryStage`	A pipeline stage that fetches instructions from a source manager.
`ExecuteStage`	Manages the hardware scheduler and issues execution-stage notifications.
`HWEventListener`	Base class for observers of MCA pipeline hardware events.
`HWInstructionDispatchedEvent`	Instruction event fired when an instruction is dispatched.
`HWInstructionEvent`	Describes a state change for an instruction that listeners may observe.
`HWInstructionIssuedEvent`	Instruction event fired when an instruction is issued to hardware resources.
`HWInstructionRetiredEvent`	Instruction event fired when an instruction is retired.
`HWPressureEvent`	An increase in backend pressure from data dependencies or resource limits.
`HWStallEvent`	A pipeline stall caused by the lack of hardware resources.
`HardwareUnit`	Base class for a simulated hardware unit used to construct an MCA backend.
`InOrderIssueStage`	Pipeline stage that issues and executes instructions in program order.
`IncrementalSourceMgr`	An implementation of SourceMgr that allows users to add new instructions incrementally / dynamically.
`InstRef`	A reference to an instruction paired with its SourceMgr index.
`InstStreamPause`	This is actually not an error but a marker to indicate that the instruction stream is paused.
`InstrBuilder`	A builder class that knows how to construct Instruction objects.
`InstrDesc`	An instruction descriptor
`InstrPostProcess`	Target hook to adjust mca::Instruction objects before the pipeline runs.
`Instruction`	An instruction propagated through the simulated instruction pipeline.
`InstructionBase`	Base class for instructions consumed by the simulation pipeline.
`InstructionError`	Error carrying a human-readable message and the instruction that failed.
`InstructionTables`	A custom pipeline stage that emits theoretical resource pressure tables.
`Instrument`	Target-specific instrumentation data attached to instructions.
`InstrumentManager`	Optional target customization of scheduling class ID resolution.
`LSUnit`	Default Load/Store Unit (LS Unit) for simulated processors.
`LSUnitBase`	Abstract base interface for LS (load/store) units in llvm-mca.
`LatencyInstrument`	Instrument that encodes an explicit instruction latency override.
`MCAOperand`	A representation of an mca::Instruction operand for use in mca::CustomBehaviour.
`MicroOpQueueStage`	A stage that simulates a queue of instruction opcodes.
`Pipeline`	A pipeline for a specific subtarget.
`PipelineOptions`	This is a convenience struct to hold the parameters necessary for creating the pre-built "default" out-of-order pipeline.
`ReadDescriptor`	A register read descriptor.
`ReadState`	Tracks register operand latency in cycles.
`RecycledInstErr`	Error indicating that an mca::Instruction was recycled rather than newly created.
`RegisterFile`	Manages hardware register files, and tracks register definitions for register renaming purposes.
`ReleaseAtCycles`	Ratio of resource cycles used to compute average pressure.
`ResourceManager`	A resource manager for processor resource units and groups.
`ResourceState`	A processor resource descriptor.
`ResourceStrategy`	Resource allocation strategy used by hardware scheduler resources.
`ResourceUsage`	Helper used by class InstrDesc to describe how hardware resources are used.
`RetireControlUnit`	Tracks which instructions are in-flight in the out-of-order backend.
`RetireStage`	Implements the retire logic of an instruction pipeline.
`Scheduler`	Class Scheduler is responsible for issuing instructions to pipeline resources.
`SchedulerStrategy`	Abstract strategy used by the Scheduler to rank ready instructions.
`SourceMgr`	Abstracting the input code sequence (a sequence of MCInst) and assigning unique identifiers to every instruction in the sequence.
`Stage`	A single stage in an instruction pipeline.
`StallInfo`	Tracks a stalled instruction and the remaining stall duration.
`View`	A view that contributes a portion of the MCA analysis report.
`WriteDescriptor`	A register write descriptor.
`WriteRef`	A reference to a register write.
`WriteState`	Tracks uses of a register definition (e.g. register write).

Type Aliases

Name	Description
`BufferUsageEntry`	Pair of a buffered resource index and the maximum buffer entries used.
`ResourceRef`	Reference to a processor resource and an optional sub-unit mask.
`ResourceRef`	A resource unit identifier.
`ResourceRef`	A resource unit identifier.
`ResourceUse`	A processor resource reference paired with its release-at-cycles cost.
`SourceRef`	Pair of a source index and the corresponding Instruction.
`UniqueInstrument`	Unique ownership wrapper for a dynamically allocated Instrument.

Enums

Name	Description
`ResourceStateEvent`	Used to notify the internal state of a processor resource.

Functions

Name	Description
`computeBlockRThroughput`	Compute the reciprocal block throughput for a code block.
`computeProcResourceMasks`	Populates vector Masks with processor resource masks.
`dumpProcResourceMasks`	Dump processor resource masks from `SM` for debugging.
`getResourceStateIndex`	Return the index of the highest bit set in `Mask.`
`operator<<`	Write InstRef `IR` to stream `OS.`

Variables

Name	Description
`UNKNOWN_CYCLES`	Sentinel latency value meaning the cycle count is not yet known.