One-sided scheduling boundary with ready queues and hazard state.
Declared in <llvm/CodeGen/VLIWMachineScheduler.h>
struct VLIWSchedBoundary;Each scheduling boundary is associated with ready queues. It tracks the current cycle in whichever direction it has moved, and maintains the state of "hazards" and other interlocks at the current cycle.
| Name | Description |
|---|---|
VLIWSchedBoundary [constructor] | Constructors |
~VLIWSchedBoundary [destructor] | Destroy hazard and resource-model state owned by this boundary. |
operator= [deleted] | Assignment is deleted; VLIWSchedBoundary is not copyable. |
bumpCycle | Advance this boundary to the next cycle and clear issue state. |
bumpNode | Account for scheduling SU at the current cycle. |
checkHazard | Return true if scheduling SU would encounter a hazard this cycle. |
init | Initialize this boundary for dag using scheduling model smodel. |
isLatencyBound | Return true if critical-path length binds scheduling of SU. |
isTop | Return true if this boundary schedules from the top of the region. |
pickOnlyChoice | Return the sole Available candidate after updating Pending, or nullptr. |
releaseNode | Release SU into Available or Pending based on ReadyCycle. |
releasePending | Move pending nodes that are ready into the Available queue. |
removeReady | Remove SU from Available or Pending if present. |
| Name | Description |
|---|---|
Available | Queue of SUnits that are ready to schedule at the current cycle. |
CheckPending | True when Pending must be drained before picking another node. |
CriticalPathLength | Estimated critical-path length used by the cost model. |
CurrCycle | Current cycle advanced by this scheduling boundary. |
DAG | Schedule DAG that owns the SUnits being scheduled from this boundary. |
HazardRec | Hazard recognizer for this scheduling direction. |
IssueCount | Micro-ops or issues counted within the current cycle. |
MaxMinLatency | Greatest minimum operand latency observed while scheduling this zone. |
MinReadyCycle | MinReadyCycle - Cycle of the soonest available instruction. |
Pending | Queue of SUnits waiting until their ready cycle or hazard clears. |
ResourceModel | VLIW packet resource model for this scheduling direction. |
SchedModel | Target scheduling model consulted for issue width and latency. |