TargetInstrInfo ‐ Interface to description of machine instruction set
Synopsis
Declared in <llvm/CodeGen/TargetInstrInfo.h>
class TargetInstrInfo
: public MCInstrInfoBase Classes
Name |
Description |
Interface to description of machine instruction set. |
Types
Name |
Description |
Represents a predicate at the MachineFunction level. The control flow a MachineBranchPredicate represents is: |
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Target‐specific loop attributes for software pipelining. |
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Pair of a register and a sub‐register index. |
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Reg:SubReg pair plus an additional sub‐register index. |
Type Aliases
Name |
Description |
Function pointer type for complex instruction deprecation checks. |
Enums
Name |
Description |
How getInstSizeInBytes results should be verified. |
Member Functions
Name |
Description |
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TargetInstrInfo is not copyable. |
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Destroy the target instruction info object. |
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TargetInstrInfo is not copyable. |
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Return true if MI defines predicate/condition‐code registers. |
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Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. |
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Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. |
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Create machine specific model for scheduling. |
Initialize MCInstrInfo, called by TableGen auto‐generated routines. DO NOT USE. |
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Convert the instruction into a predicated instruction. It returns true if the operation was successful. |
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Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest. This is used by the tail merging pass. |
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Returns true if the first specified predicate subsumes the second, e.g. GE subsumes GT. |
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When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency. |
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Analyze branching at the end of MBB into TBB, FBB, and Cond. |
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Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible. Returns false on success and true on failure. |
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Analyze comparison MI into source registers, mask, and value. |
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Analyze loop L for induction variable and compare instruction. |
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Analyze loop L, which must be a single‐basic‐block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. |
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Return true if Load1 and Load2 share a base pointer with different offsets. |
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Return true if MIa and MIb access disjoint memory without alias info. |
Return true when P Opcode1 or its inversion is equal to P Opcode2. |
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Insert a dependency‐breaking instruction before MI to eliminate an unwanted dependency on OpNum. |
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Insert a target‐specific instruction that clears Reg. |
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Insert a custom frame for outlined functions. |
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Return true if the given SDNode can be copied during scheduling even if it has glue. |
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Return true if AddrI can be folded into MemI's addressing mode. |
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Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond. |
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Returns true if the tail call can be made conditional on BranchCond. |
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Assumes the instruction is already predicated and returns true if the instruction can be predicated again. |
This method commutes the operands of the given machine instruction MI. |
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Convert a two‐address MI into true three‐address instructions if possible. |
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Emit instructions to copy a pair of physical registers. |
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Return a MIR printer comment string for operand Op of MI. |
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During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner. |
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During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner. |
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Decompose the machine operand's target flags into two values ‐ the direct target flag value and any of bit flags that are applied. |
Return the default expected latency for a def based on its opcode. |
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Describe the value MI loads into physical register Reg. |
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Clones instruction or the whole instruction bundle |
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Emit a load/store like MemI using addressing mode AM. |
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Expand post‐RA pseudo instruction MI into real instructions. |
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Return the increase in code size needed to predicate a contiguous run of NumInsts instructions. |
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Fix up the placeholder we may add in genAlternativeCodeSequence(). |
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Find two commutable operand indices in MI. |
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Try to fold an immediate defined by DefMI into use UseMI. |
Fold a load/store into MI for the given operands. |
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Generate alternative instructions for a machine‐combiner pattern. |
Return the machine instruction descriptor that corresponds to the specified instruction opcode. |
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Returns an opcode which defines the accumulator used by P Opcode. |
Find the chain of accumulator instructions in P MBB and return them in P Chain. |
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Find chains of accumulations that can be rewritten as a tree for increased ILP. |
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Extract an ExtAddrMode description from memory instruction MemI. |
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Return true if MI has base/offset operands, setting their positions. |
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Return the basic block that branch instruction MI jumps to. |
Return the opcode of the call‐frame destroy instruction, or ‐1. |
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Return the opcode of the call‐frame setup instruction, or ‐1. |
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Return the call frame size immediately before MI. |
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Returns the callee operand from the given |
Return the catch‐return opcode used by this target. |
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Return the objective of a combiner pattern. |
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Return true if MI defines Reg to a constant recorded in ImmVal. |
Returns true if a certain instruction is deprecated and if so returns the reason in |
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Return the current execution domain and bit mask of possible domains for instruction. |
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The limit on resource length extension we accept in MachineCombiner Pass. |
Build EXTRACT_SUBREG‐equivalent inputs for MI at DefIdx. |
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Fill Ops with machine operands that refer to frame index FI. |
Return the frame size associated with the given frame instruction. |
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Return the total frame size including space set up before the frame pair. |
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If the instruction is an increment of a constant value, return the amount. |
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Measure the specified inline asm to determine an approximation of its length. |
Build INSERT_SUBREG‐equivalent inputs for MI at DefIdx. |
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Sum getInstSizeInBytes over instructions inside a BUNDLE. |
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For BUNDLE instructions, target implementations are responsible for accounting for the size of all bundled instructions. |
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Determine whether/how the instruction size returned by getInstSizeInBytes() should be verified. |
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Return the inverse operation opcode if it exists for P Opcode (e.g. add for sub and vice versa). |
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Return an index for MachineJumpTableInfo if |
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Allows targets to use appropriate copy instruction while spilitting live range of a register in register allocation. |
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Return MIR formatter to format/parse MIR operands. Target can override this virtual function and return target specific MIR formatter. |
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Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs. |
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Collect machine‐combiner patterns ending at Root. |
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Return a strategy that MachineCombiner must use when creating traces. |
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Return the max product of memory operands checked for aliasing. |
Get a single base operand and byte offset for memory instruction MI. |
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Get base operands, offset, and access width for memory instruction MI. |
Returns the name for the instructions with the given opcode. |
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Return the noop instruction to use for a noop. |
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Return how many micro‐ops MI decodes to on the target CPU. |
Return the number of instruction opcodes described by this info. |
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Return the opcode after unfolding load/store from Opc, or zero. |
Compute use‐operand latency between a def and a use. |
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Optional target hook which partitions |
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Return outlining info for RepeatedSequenceLocs, or nullopt if unsuitable. |
Returns how or if |
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Returns the preferred minimum clearance before an instruction with an unwanted partial register update. |
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Return the operand range that cannot be folded for patchpoint‐like MI. |
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Return the extra cost of predicating MI. |
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Fill OperandIndices with reassociation operand positions for Pattern. |
Return new root/prev opcodes required to reassociate Pattern. |
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Returns the opcode that should be use to reduce accumulation registers. |
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Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL. |
Return the register‐class lookup row for the given hardware mode. |
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Build REG_SEQUENCE‐equivalent inputs for MI at DefIdx. |
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Return the target register info associated with this instruction info. |
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Return the return opcode used by this target. |
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Return the stack‐pointer adjustment made by MI as part of a call sequence. |
Return an array that contains the bitmask target flag values and their names. |
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Return an array that contains the direct target flag values and their names. |
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Return an array that contains the MMO target flag values and their names. |
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Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names. |
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Compute the size in bytes and offset within a stack slot of a spilled register or subregister. |
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Returns the target‐specific default value for tail duplication. This value will be used if the tail‐dup‐placement‐threshold argument is not provided. |
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Returns the target‐specific default value for tail merging. This value will be used if the tail‐merge‐size argument is not provided. |
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Return the minimum clearance before an instruction that reads an unused register. |
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Return the uniformity behavior of the given value. |
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Return true if the target prefers a specific operand order for MI. |
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Return true if the def‐use operand latency is considered high. |
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Return true if MI loads from a stack slot, collecting mem operands. |
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Compute operand latency of a def of 'Reg'. Return true if the target considered it 'low'. |
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Return true when P Inst has reassociable operands in the same P MBB. |
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Return true when P Inst has reassociable sibling. |
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Return true if MI stores to a stack slot, collecting mem operands. |
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Insert branch code at the end of MBB for TBB/FBB/Cond. |
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Insert a code prefetch instruction targeting GV before InsertBefore in MBB. |
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Insert an unconditional indirect branch from MBB to NewDestBB. |
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Insert a noop into the instruction stream at the specified point. |
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Insert noops into the instruction stream at the specified point. |
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Insert a call to an outlined function into the program. Returns an iterator to the spot where we inserted the call. This must be implemented by the target. |
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Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false. |
Insert an unconditional branch from MBB to DestBB. |
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Return true when P OpCode is an instruction which performs accumulation into one of its operand registers. |
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Return source register and immediate if MI defines Reg as Reg+Imm. |
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Return true if the instruction is as cheap as a move instruction. |
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Return true when P Inst is both associative and commutative. If P Invert is true, then the inverse of P Inst operation must be tested. |
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Return true if MI must remain at the top of its basic block. |
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Return true if BranchOpc can reach a displacement of BrOffset bytes. |
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Return true if MI is a coalescable extension instruction. |
Return destination and source operands if MI is a copy. |
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Return destination and source operands if MI is copy‐like. |
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Return true if MI defines a trackable TargetIndex operand. |
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Given the generic extension instruction |
Returns true if the argument is a frame pseudo instruction. |
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Returns true if the argument is a frame setup pseudo instruction. |
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Return true if MI is a full‐register copy with no subregs. |
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Return true if MF can safely be outlined from. |
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Return true if the function is a viable candidate for machine function splitting. The criteria for if a function can be split may vary by target. |
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Returns true if MI is an instruction we are unable to reason about (like a call or something with unmodeled side effects). |
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Return true if this opcode has high latency to its result. |
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Given |
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Return true if it's legal to split the given basic block at the specified instruction (i.e. instruction would be the start of a new basic block). |
Return the destination register if MI loads directly from a stack slot. |
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Check for post‐frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness. |
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Optional target hook that returns true if |
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Return true if MBB can safely be split to the cold section. |
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Return true if MO may participate in PC‐relative addressing. |
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Return true for post‐incremented instructions. |
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Return true if the specified instruction can be predicated. By default, this returns true for every instruction with a PredicateOperand. |
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Returns true if the instruction is already predicated. |
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Return true if duplicating MBB instructions for if‐conversion is profitable. |
Return true if predicating the block(s) for if‐conversion is profitable. |
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Return true if unpredicating one side of a diamond is profitable. |
Return true if MI would be rematerializable where its uses are live. |
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Return true if Inst is part of a reassociable dependent chain. |
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Return true if it is safe to move MI. |
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Return true if it's safe to move a machine instruction that defines the specified register class. |
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Return true if MI is safe to sink into SuccToSinkTo. |
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Test if the given instruction should be considered a scheduling boundary. This primarily includes labels and terminators. |
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Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect. Provide the identity of the two frame indices. |
Return the source register if MI stores directly to a stack slot. |
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Check for post‐frame ptr elimination stack locations as well. This uses a heuristic, so it isn't reliable for correctness. |
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Return true if the target can fold loads/stores through subreg operands. |
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Return true if Inst is a tail call instruction. |
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Return true when a code sequence can improve throughput. It should be called only for instructions in loops. |
Return true if MI is trivially rematerializable. |
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Returns true if MI is an unconditional tail call. |
Returns true if the instruction is a terminator instruction that has not been predicated. |
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Return true if the given instruction is terminator that is unspillable, according to isUnspillableTerminatorImpl. |
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Return true if Opcode is a pseudo that consumes no machine resources. |
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Load DestReg of class RC from stack frame FrameIndex before MI. |
This function defines the logic to lower COPY instruction to target specific instruction(s). |
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Optional target hook to create the LLVM IR attributes for the outlined function. If overridden, the overriding function must call the default implementation. |
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Try to optimize comparison CmpInstr into a more efficient form. |
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Try to optimize conditional branch MI. |
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Try to fold a load into a register operand of use MI. |
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Given an instruction marked as |
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Return an estimate for the code size reduction (in bytes) which will be caused by removing the given branch instruction during if‐conversion. |
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Return true if MI preserves a zero value in NullValueReg. |
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Return true if MI0 and MI1 would produce identical values. |
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Re‐issue Orig at MI targeting DestReg:SubIdx. |
Attempt to reassociate P Root and P Prev according to P Pattern to reduce critical path length. |
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Reduces branches of the accumulator tree into a single register. |
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Generate code that reduces the loop count and tests completion. |
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Remove branching instructions at the end of MBB. |
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Replace the conditional branch in MBB with a conditional tail call. |
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Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed. |
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Change the opcode of MI to execute in Domain. |
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This is an architecture‐specific helper function of reassociateOps. Set special operand attributes for new instructions after reassociation. |
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For a "cheap" instruction which doesn't enable additional sinking, should MachineSink break a critical edge to sink it anyways? |
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Return true if the two memory operations should be scheduled adjacent. |
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Return false if the instruction should not be hoisted by MachineLICM. |
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Return true if the function should be outlined from by default. |
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Return true if MI should be sunk by PostRAMachineSink. |
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Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB. |
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Return true if nearby loads should be scheduled together. |
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Return true if the instruction should be sunk by MachineSink. |
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If possible, converts the instruction to a simplified/canonical form. Returns true if the instruction was modified. |
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Store SrcReg of class RC to stack frame FrameIndex before MI. |
Unfold a folded load/store into separate instructions or nodes. |
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Return true when a target supports MachineCombiner. |
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor. |
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Perform target‐specific instruction verification. |
Static Member Functions
Name |
Description |
Return true if Opc is a generic atomic RMW TargetOpcode. |
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Return true if Opc is a generic TargetOpcode value. |
Static Data Members
Name |
Description |
Sentinel meaning findCommutedOpIndices may pick any operand index. |
Protected Member Functions
Name |
Description |
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Construct target instruction info for the given register info and opcodes. |
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This method commutes the operands of the given machine instruction MI. The operands to be commuted are specified by their indices OpIdx1 and OpIdx2. |
Target‐specific implementation of foldMemoryOperand. |
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Target‐dependent implementation of getExtractSubregInputs. |
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Target‐dependent implementation of getInsertSubregInputs. |
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Target‐dependent implementation for getOutliningTypeImpl. |
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Target‐dependent implementation of getRegSequenceInputs. |
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Target‐specific implementation of isCopyInstr. |
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Target‐specific implementation of isCopyLikeInstr. |
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Return true if a rematerializable‐flagged MI is actually rematerializable. |
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Return true if terminator MI should not spill. |
Protected Static Member Functions
Name |
Description |
Assign a pair of commutable operand indices into ResultIdx1/ResultIdx2. |
Protected Data Members
Name |
Description |
Number of register‐class entries per hardware mode in the lookup tables. |
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Subtarget‐specific RegClassByHwMode table for the active HwMode. |
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Flattened [NumHwModes][NumRegClassByHwModes]register‐class lookup tables. |
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Target register info for the subtarget that owns this instruction info. |
Non-Member Functions
Name |
Description |
Create a DAG mutation that constrains copies near their uses/defs. |
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Create a DAG mutation that clusters loads for better memory locality. |
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Create a DAG mutation that clusters stores for better memory locality. |
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