Scheduled code for a software‐pipelined loop.

Synopsis

Declared in <llvm/CodeGen/MachinePipeliner.h>

class SMSchedule;

Description

The main data structure is a map from scheduled cycle to instructions. During scheduling, the data structure explicitly represents all stages/iterations. When the algorithm finishes, the schedule is collapsed into a single stage, which represents instructions from different loop iterations.

The SMS algorithm allows negative values for cycles, so the first cycle in the schedule is the smallest cycle value.

Type Aliases

Name

Description

const_sched_iterator

Const iterator over the cycle‐to‐instruction map.

sched_iterator

Iterators for the cycle to instruction map.

Member Functions

Name

Description

SMSchedule [constructor]

Construct a schedule for mf using dependence info from DAG.

computeStart

Compute earliest and latest legal start cycles for SU.

computeUnpipelineableNodes

Compute nodes that cannot be pipelined for this loop.

cycleScheduled

Return the cycle for a scheduled instruction. This function normalizes the first cycle to be 0.

dump

Dump the schedule to the debug stream.

finalizeSchedule

Collapse stages into a final kernel schedule and apply instruction fixes.

getFinalCycle

Return the last cycle in the finalized schedule.

getFirstCycle

Return the first cycle in the completed schedule. This can be a negative value.

getInitiationInterval

Return the initiation interval for this schedule.

getInstructions

Return the instructions that are scheduled at the specified cycle.

getMaxStageCount

Return the maximum stage count needed for this schedule.

insert

Try to schedule SU in []`StartCycle,` EndCycle) at II II.

isLoopCarried

Return true if PHI Phi has a loop‐carried dependence in this schedule.

isLoopCarriedDefOfUse

Return true if Def is a loop‐carried definition of use operand MO.

isScheduledAtStage

Return true if the instruction is scheduled at the specified stage.

isValidSchedule

Return true if the current schedule satisfies dependence constraints.

normalizeNonPipelinedInstructions

Place unpipelineable instructions into a legal single‐iteration region.

onlyHasLoopCarriedOutputOrOrderPreds

Return true if SU has only loop‐carried output or order predecessors.

orderDependence

Insert SU into Insts in an order consistent with dependences.

print

Print the schedule to os.

reorderInstructions

Reorder Instrs to respect dependence constraints from SSD.

reset

Clear scheduled instructions and reset cycle and II state.

setInitiationInterval

Set the initiation interval for this schedule.

stageScheduled

Return the stage for a scheduled instruction. Return ‐1 if the instruction has not been scheduled.

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